Typical prior art NMOS devices usually handle the least voltage of all the devices in a BiCMOS process. This is due to the ability of the device to easily avalanche and cause excess electron flow, the electron being the majority carrier for this device. Additionally, in a typical CMOS process, (P substrate), this device must have its back-gate tied to substrate, causing undesirable threshold voltage shifting due to the body-effect when the source is raised in potential above the substrate. Lastly, NMOS devices typically have a lower output impedance per unit of channel length than do PMOS devices, again due to the ability of the N type drain material to create a strong depletion region. Low output impedance is generally undesirable as it causes non-linearities in analog circuitry.
Often it is necessary to achieve higher voltages than a normal CMOS process typically allows. Additionally, in linear circuits, especially when source-followers are needed, the increased threshold voltage created by back-gate tied to a P-substrate while the source goes to a positive voltage (body effect) can cause loss of headroom. Also, a device, especially in source followers, can often need to have a low threshold voltage to achieve headroom. Lastly, the output impedance of shorter channel NMOS devices can be lower than desired.